Sandy Bridge Known as Gesher
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Sandy Bridge (formerly known as Gesher) is the
codename of the tenth generation of the x86 architecture developed by Intel for
its microprocessors going to happen ninth generation Nehalem architecture,
contrary to its evolution to 32 nm Westmere.
This architecture debuted January 9, 2011.
Sandy Bridge provides processors made using 32 nm production process and available in various sizes up to 8 cores and operating at frequencies that are expected to reach the historic barrier of 4 GHz is envisaged that the allocation of cache for each core is 80 KB for L1 (with a read time of 3 clock cycles), 256 KB L2 for (8 cycles).
Initially there was talk also of a 512-KB L2 cache and L3 2-3 MB per core (from 33 cycles), for a total of no less than 24 MB of L3 cache and an 8-core processor. Later it was learned, however, that the approach of the cache will be very similar to the Nehalem architecture, and then the L1 and L2 to be exclusive access to each core, while the L3 is a single shared and dynamically allocated across all cores, in a manner so different from what happened with the L2 architecture "Core" Core 2 Duo processor where it was unique for each pair of cores, but as is the case in the architecture that is ahead of Sandy Bridge, the aforementioned Nehalem. In fact, as Nehalem is inspired by the former "core" improving different aspects, so many choices Sandy Bridge will resume Nehalem architecture introduced with refined due to technological progress, but needs a new type of socket (LGA 1155) [1].
For the variant 4-Core L3 cache is 6 or 8 MB shared between all cores, but his speed should increase to a reading time of only 25 clock cycles, compared to 33 originally announced.
It is obviously still present DDR3 memory controller capable of providing a bandwidth of 64 GB / s, while that of the Common System Interface bus (renamed Intel QuickPath Interconnect architecture Nehalem at launch) will be of 17 GB / s. Processors based on Sandy Bridge are in possession of computing power for over 28 per core GigaFLOPS getting up to 112-224 GigaFLOPS then for each processor complete (depending on whether 4 or 8 cores), thanks to the presence of technology Simultaneous Multi-Threading, introduced in Nehalem.
Once again (as is already the case for the previous architectures "Core" and Nehalem), the main objective is to limit fuel consumption or better overall efficiency of the entire architecture: performance is increased without resorting to core larger than those of previous processors, and also a mode called "Dynamic Turbo" allows the CPU to exceed the maximum expected value in the factory when the rest of the system is in a state very "fresh" in that mode, the clock is increased with peaks of 37% for about a minute and average values of 20% for even longer time. This feature reminds many ways Intel's Turbo Mode technology introduced in the Nehalem-based processors.
It is currently anticipated that the various models of the clock source can vary from 1.8 GHz to 3.4 GHz thanks to the Dynamic Turbo that can be brought to values from 3.5 GHz to 4.8 well GHz (although for a short time).
It should be noted that some technical features planned for Sandy Bridge are similar to those designed for the project Keifer, a processor announced by Intel in 2006 and that was to become a well-32 CPU cores in 2010. Probably the project in question was suspended, but some design ideas are then merged into the new architecture, among these we may mention a new type of "Ring Bus" 256-bit cores should interconnect with each other.
SANDY BRIDGE
This architecture debuted January 9, 2011.
Sandy Bridge provides processors made using 32 nm production process and available in various sizes up to 8 cores and operating at frequencies that are expected to reach the historic barrier of 4 GHz is envisaged that the allocation of cache for each core is 80 KB for L1 (with a read time of 3 clock cycles), 256 KB L2 for (8 cycles).
Initially there was talk also of a 512-KB L2 cache and L3 2-3 MB per core (from 33 cycles), for a total of no less than 24 MB of L3 cache and an 8-core processor. Later it was learned, however, that the approach of the cache will be very similar to the Nehalem architecture, and then the L1 and L2 to be exclusive access to each core, while the L3 is a single shared and dynamically allocated across all cores, in a manner so different from what happened with the L2 architecture "Core" Core 2 Duo processor where it was unique for each pair of cores, but as is the case in the architecture that is ahead of Sandy Bridge, the aforementioned Nehalem. In fact, as Nehalem is inspired by the former "core" improving different aspects, so many choices Sandy Bridge will resume Nehalem architecture introduced with refined due to technological progress, but needs a new type of socket (LGA 1155) [1].
For the variant 4-Core L3 cache is 6 or 8 MB shared between all cores, but his speed should increase to a reading time of only 25 clock cycles, compared to 33 originally announced.
It is obviously still present DDR3 memory controller capable of providing a bandwidth of 64 GB / s, while that of the Common System Interface bus (renamed Intel QuickPath Interconnect architecture Nehalem at launch) will be of 17 GB / s. Processors based on Sandy Bridge are in possession of computing power for over 28 per core GigaFLOPS getting up to 112-224 GigaFLOPS then for each processor complete (depending on whether 4 or 8 cores), thanks to the presence of technology Simultaneous Multi-Threading, introduced in Nehalem.
Once again (as is already the case for the previous architectures "Core" and Nehalem), the main objective is to limit fuel consumption or better overall efficiency of the entire architecture: performance is increased without resorting to core larger than those of previous processors, and also a mode called "Dynamic Turbo" allows the CPU to exceed the maximum expected value in the factory when the rest of the system is in a state very "fresh" in that mode, the clock is increased with peaks of 37% for about a minute and average values of 20% for even longer time. This feature reminds many ways Intel's Turbo Mode technology introduced in the Nehalem-based processors.
It is currently anticipated that the various models of the clock source can vary from 1.8 GHz to 3.4 GHz thanks to the Dynamic Turbo that can be brought to values from 3.5 GHz to 4.8 well GHz (although for a short time).
It should be noted that some technical features planned for Sandy Bridge are similar to those designed for the project Keifer, a processor announced by Intel in 2006 and that was to become a well-32 CPU cores in 2010. Probably the project in question was suspended, but some design ideas are then merged into the new architecture, among these we may mention a new type of "Ring Bus" 256-bit cores should interconnect with each other.
SANDY BRIDGE
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